CO · Section 3: Computer Organization and Architecture
Computer Organization & Architecture
Machine instructions and addressing modes, ALU, data path and control unit, pipelining, memory hierarchy and I/O.
Topics
7 topics in syllabus order, each with study material.
Instruction formats and field widths, counting instructions with expanding opcodes, zero- to three-address code, instruction types, RISC versus CISC, condition flags, byte ordering and alignment, and every addressing mode with its effective-address rule, memory-reference count and typical use.
Ripple-carry and carry-lookahead adders with gate-delay counts, the adder-subtractor, overflow logic and flags, array and Booth multiplication, shifters, and the single-bus and three-bus datapaths with the register transfers and control steps of fetch and execute.
Hardwired control from a step counter, decoders and sum-of-products signal equations; microprogrammed control with control words, horizontal and vertical microinstructions, control-memory size calculations, microinstruction sequencing and a short note on nanoprogramming.
Building a memory from smaller chips: chip counts, decoders, address maps, partial decoding, DRAM address multiplexing and interleaving. Then locality, hit ratio and average access time for hierarchical and simultaneous access, multilevel formulas and memory stall cycles.
Direct, set-associative and fully associative mapping, the tag, index and offset split, tag-memory size and lookup hardware, traced reference strings with LRU and FIFO, the three miss types, array traversal misses, write-through and write-back with allocation policies, and multilevel caches.
I/O interfaces, memory-mapped and isolated I/O, programmed I/O, the interrupt sequence, vectored and daisy-chain priority, masking and nesting, CPU overhead of polling and interrupts, and DMA: controller, bus handshake, burst, cycle-stealing and transparent modes with CPU-time fractions.
Pipeline clock from stage and latch delays, total time, speedup, efficiency, throughput and CPI; data hazards with space-time diagrams, stalls and forwarding; control hazards with branch penalties, prediction and delay slots; structural hazards and combined CPI.
Computer Organization revision: traps, patterns and last day
The last three sheets: traps that cost marks with the rule that fixes each, question patterns with the routine to run, and a one-page master sheet of formulas, tables and numbers to recognise.