Direct Memory Access (DMA)

Direct memory access (DMA) lets an I/O interface move a block of data between a device and main memory without the processor handling each word. The processor programs a DMA controller with a memory address, a word count and a direction, and goes back to other work; the controller takes control of the system bus when it needs it, transfers the words, and normally raises one completion interrupt when enabled; completion may instead be polled.

GATE asks you to compute the fraction of time the processor is held off the bus under burst and cycle-stealing DMA, to compare DMA with interrupt-driven and programmed I/O for the same device, to work out block transfer times, and to describe how the bus is handed between the processor and the DMA controller. Programmed and interrupt-driven I/O are covered in I/O Interface and Interrupts.

A controller may have several channels, each with its own set of registers, so several devices can share it.

The processor can be held off the bus in the middle of an instruction, at any bus cycle boundary, unlike an interrupt, which waits for the instruction to finish: DMA only borrows bus cycles and does not need the processor's registers.

When several masters (the processor and DMA controllers) can drive the bus, an arbiter decides who gets it. In centralised arbitration, one arbiter receives the requests; the grant may be daisy-chained, so the controller nearest the arbiter has the highest priority, exactly as with interrupt acknowledge. In distributed arbitration, the masters compare their priority codes on shared lines and the highest wins without a central arbiter.

With interrupt-driven I/O the processor pays for an interrupt per unit of transfer; with DMA it pays one set-up per block and normally one completion interrupt when enabled (or a polling cost instead). The only remaining cost is bus contention: each word moved by DMA occupies one bus cycle that the processor might have wanted.

This pseudocode uses word addresses, so +1 advances one word; count is in words. For byte-addressable memory, advance the address by the number of bytes per word instead.

Cycle stealing. If the device transfers at $R$ bytes per second in words of $w$ bytes, and each steal holds the bus for $t_c$ seconds, the fraction of bus time taken is

That is the processor's worst-case slowdown, reached only if it needs the bus in every cycle.

Burst mode with a buffered device. If the device fills a buffer of $B$ bytes at rate $R$ (taking $t_{\text{prep}} = B / R$) and the controller then empties it in a burst taking $t_{\text{tx}}$, the processor is blocked for

of the time, when preparation and transfer do not overlap.

Overlapped preparation. If the device prepares the next unit while the controller moves the previous one (and the move is the shorter of the two), a new unit is ready every $t_{\text{prep}}$, so the cycle length is $t_{\text{prep}}$ and the processor is blocked for

of the time. The same two formulas apply per word in cycle-stealing mode, with $t_{\text{prep}}$ the time the device needs per word and $t_{\text{tx}}$ one stolen bus cycle. Read whether the question lets preparation and transfer overlap: the two answers are close when $t_{\text{tx}} \ll t_{\text{prep}}$ but are not equal.

Processor cost per block. Set-up cycles $+$ completion interrupt cycles, paid $R / B$ times per second; as a fraction of a clock of $f$ Hz:

A disk delivers 8 MB/s ($8 \times 10^6$ bytes per second) to a 2 GHz processor. With interrupts per 16-byte unit at 1000 cycles each, the processor spends 25% of its time (see I/O Interface and Interrupts). With DMA in 4 KB (4096-byte) blocks, 1000 cycles of set-up and 500 cycles for the completion interrupt:

A device transfers 2 MB/s in 4-byte words by cycle stealing; each steal takes one 100 ns bus cycle. Steals per second: $2 \times 10^6 / 4 = 5 \times 10^5$, occupying $5 \times 10^5 \times 100$ ns $= 0.05$ s per second, so 5% of bus time. If the processor needs the bus in only 40% of its cycles and the steals fall independently of its bus use, about 40% of the steals collide with a processor bus cycle, so it loses about $0.4 \times 5\% = 2\%$ of its cycles; 5% is the worst case.

A device fills a 2000-byte buffer at 1 MB/s ($10^6$ bytes per second), then the controller empties it into memory over a 100 MB/s bus in burst mode. Preparation: $2000 / 10^6 = 2$ ms. Transfer: $2000 / 10^8 = 20\ \mu$s. The processor is blocked for $20 / (2000 + 20) \approx 0.99\%$ of the time. If the device keeps filling a second buffer while the first is being emptied, a burst starts every 2 ms and the blocked fraction is $20 / 2000 = 1\%$.

The same device-paced reasoning per word: a device that prepares one word every 2 $\mu$s, with each steal taking 50 ns, blocks the processor for $50/2000 = 2.5\%$ of the time if preparation overlaps the steal, and $50/2050 \approx 2.44\%$ if the device waits for each steal to finish before preparing the next word.

A block of 4 words is moved during 16 bus cycles. The processor needs the bus in every cycle except 3, 7, 11 and 15 (when it is executing internally).

Burst delivers the block soonest (by cycle 4); transparent delivers it last (cycle 15) but costs the processor nothing.

A 512-word block moves by cycle stealing, one word every 10 bus cycles of 50 ns (the device's pace). The last word moves 511 periods after the first, so the transfer spans $511 \times 10 + 1 = 5111$ bus cycles $\approx 255.6\ \mu$s, of which only 512 cycles (25.6 $\mu$s) are taken from the processor.

Related material. DMA reads and writes main memory directly. If a cache holds a copy of a line that DMA overwrites, the processor would read stale data; if a write-back cache holds a dirty line that DMA reads from memory, the device would get stale data. Systems either flush or invalidate the affected lines in software before and after DMA, or let the cache snoop DMA bus traffic.