Digital Logic

Topics

• Boolean Algebra and Logic Minimization 37
• Combinational Circuits 22
• Sequential Circuits, Counters and Registers 20
• Number Representations and Computer Arithmetic 35

All Digital Logic questions

1. GATE CS 2026 Set 1MSQ1 markEasy (estimate)

   GATE CS 2026 Set 1, Q.21

   Consider the following Boolean expression of a function $F$ : $F(P,Q)=(\overline{P}+Q)\oplus (\overline{P}Q)$ Which of the following expressions is/are equivalent to $F$ ?

   Boolean Algebra and Logic Minimization

2. GATE CS 2026 Set 1MSQ1 markEasy (estimate)

   GATE CS 2026 Set 1, Q.22

   Consider the 8-bit signed integers $X$, $Y$ and $Z$ represented using the sign-magnitude form. The binary representations of $X$ and $Y$ are as follows…

   Number Representations and Computer Arithmetic

3. GATE CS 2026 Set 1MCQ2 marksMedium (estimate)

   GATE CS 2026 Set 1, Q.37

   Consider a 2-bit saturating up/down counter that performs the saturating up count when the input $P$ is 0, and the saturating down count when $P$ is 1. The Next State table of t...

   Sequential Circuits, Counters and Registers

4. GATE CS 2026 Set 1MSQ2 marksMedium (estimate)

   GATE CS 2026 Set 1, Q.48

   Consider a Boolean function $F$ with the following minterm expression: $F(P,Q,R,S)=\sum m(1,2,3,4,5,7,10,12,13,14)$ Which of the following options is/are the min...

   Boolean Algebra and Logic Minimization

5. GATE CS 2026 Set 2MCQ1 markEasy (estimate)

   GATE CS 2026 Set 2, Q.16

   Which one of the following options is not a property of Boolean Algebra? Note: $+$ is OR operation, $.$ is AND operation, and ${}^{\prime }$ is NOT operation

   Boolean Algebra and Logic Minimization

6. GATE CS 2026 Set 2MSQ1 markEasy (estimate)

   GATE CS 2026 Set 2, Q.28

   In a system, numbers are represented using 4-bit two's complement form. Consider four numbers $N_1=1011$, $N_2=1101$, $N_3=1010$ and $N_4=1001$ in the system. Which of t...

   Number Representations and Computer Arithmetic

7. GATE CS 2026 Set 2NAT1 markEasy (estimate)

   GATE CS 2026 Set 2, Q.34

   The 32-bit IEEE 754 single precision representation of a number is 0xC2710000. The number in decimal representation is ________. (rounded off to two decimal places)

   Number Representations and Computer Arithmetic

8. GATE CS 2026 Set 2MCQ2 marksEasy (estimate)

   GATE CS 2026 Set 2, Q.40

   Consider the following 4-variable Boolean function $F(A,B,C,D)=\Sigma m(0,1,2,3,8,9,10,11)$ Consider $A$ as MSB, $D$ as LSB. Which one of the following options rep...

   Boolean Algebra and Logic Minimization

9. GATE CS 2026 Set 2NAT2 marksEasy (estimate)

   GATE CS 2026 Set 2, Q.59

   Consider the digital circuit shown below with two input lines A and B, two select lines S0 and S1, and an output line Y. The blocks Q and M represent active high 2:4 decoder and...

   Combinational Circuits

10. GATE CS 2025 Set 1MSQ1 markMedium (estimate)

    GATE CS 2025 Set 1, Q.24

    Let $X$ be a 3-variable Boolean function that produces output as '1' when at least two of the input variables are '1'. Which of the following statement(s) is/are CORRECT, where...

    Boolean Algebra and Logic Minimization

11. GATE CS 2025 Set 1MSQ1 markEasy (estimate)

    GATE CS 2025 Set 1, Q.25

    The number $-6$ can be represented as $1010$ in 4-bit 2's complement representation. Which of the following is/are CORRECT 2's complement representation(s) of $-6$?

    Number Representations and Computer Arithmetic

12. GATE CS 2025 Set 1MCQ2 marksEasy (estimate)

    GATE CS 2025 Set 1, Q.42

    Consider the following four variable Boolean function in sum-of-product form $F(b_3,b_2,b_1,b_0)=\sum (0,2,4,8,10,11,12).$ where the value of the function is compute...

    Boolean Algebra and Logic Minimization

13. GATE CS 2025 Set 1NAT2 marksMedium (estimate)

    GATE CS 2025 Set 1, Q.59

    Consider a finite state machine (FSM) with one input $X$ and one output $f$, represented by the given state transition table. The minimum number of states required to realize th...

    Sequential Circuits, Counters and Registers

14. GATE CS 2025 Set 1NAT2 marksMedium (estimate)

    GATE CS 2025 Set 1, Q.60

    Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go...

    Sequential Circuits, Counters and Registers

15. GATE CS 2025 Set 2MSQ1 markEasy (estimate)

    GATE CS 2025 Set 2, Q.31

    Consider the following logic circuit diagram. Logic circuit with inputs Y and X feeding three branches into a 3-input OR gate with output F: top branch is a 2-input NAND gate of...

    Boolean Algebra and Logic Minimization · Combinational Circuits

16. GATE CS 2025 Set 2NAT1 markEasy (estimate)

    GATE CS 2025 Set 2, Q.34

    In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is ________. (Answer in integer)

    Sequential Circuits, Counters and Registers

17. GATE CS 2025 Set 2MSQ2 marksEasy (estimate)

    GATE CS 2025 Set 2, Q.43

    Given the following Karnaugh Map for a Boolean function $F(w,x,y,z)$: 4 by 4 Karnaugh Map for F(w, x, y, z) with row variables wx and column variables yz; rows 1 and 4 are 1,...

    Boolean Algebra and Logic Minimization

18. GATE CS 2025 Set 2MSQ2 marksMedium (estimate)

    GATE CS 2025 Set 2, Q.50

    Which of the following Boolean algebraic equation(s) is/are CORRECT?

    Boolean Algebra and Logic Minimization

19. GATE CS 2024 Set 1MCQ1 markEasy (estimate)

    GATE CS 2024 Set 1, Q.13

    Consider a system that uses 5 bits for representing signed integers in 2's complement format. In this system, two integers $A$ and $B$ are represented as $A=01010$ and $B=11010$...

    Number Representations and Computer Arithmetic

20. GATE CS 2024 Set 1MSQ1 markMedium (estimate)

    GATE CS 2024 Set 1, Q.28

    Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of th...

    Combinational Circuits

21. GATE CS 2024 Set 1MSQ2 marksEasy (estimate)

    GATE CS 2024 Set 1, Q.47

    Consider a Boolean expression given by $F(X,Y,Z)=\sum (3,5,6,7)$. Which of the following statements is/are CORRECT?

    Boolean Algebra and Logic Minimization

22. GATE CS 2024 Set 1NAT2 marksEasy (estimate)

    GATE CS 2024 Set 1, Q.64

    Consider a digital logic circuit consisting of three 2-to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are inputs of M2. A, B, and C are s...

    Combinational Circuits

23. GATE CS 2024 Set 2MSQ1 markEasy (estimate)

    GATE CS 2024 Set 2, Q.30

    For a Boolean variable $x$, which of the following statements is/are FALSE?

    Boolean Algebra and Logic Minimization

24. GATE CS 2024 Set 2MSQ2 marksEasy (estimate)

    GATE CS 2024 Set 2, Q.49

    Which of the following is/are EQUAL to 224 in radix-5 (i.e., base-5) notation?

    Number Representations and Computer Arithmetic

25. GATE CS 2024 Set 2MSQ2 marksEasy (estimate)

    GATE CS 2024 Set 2, Q.50

    Consider 4-variable functions $f1,f2,f3,f4$ expressed in sum-of-minterms form as given below. $f1=\sum (0,2,3,5,7,8,11,13)$ $f2=\sum (1,3,5,7,11,13,15)$…

    Combinational Circuits · Boolean Algebra and Logic Minimization

26. GATE CS 2023MCQ1 markMedium (estimate)

    GATE CS 2023, Q.21

    The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. A 2-input multiplexer with inputs 0 and 1, select line S, and output Q connect...

    Combinational Circuits · Sequential Circuits, Counters and Registers

27. GATE CS 2023NAT1 markEasy (estimate)

    GATE CS 2023, Q.32

    A particular number is written as $132$ in radix-$4$ representation. The same number in radix-$5$ representation is _______.

    Number Representations and Computer Arithmetic

28. GATE CS 2023MCQ2 marksMedium (estimate)

    GATE CS 2023, Q.43

    Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At the beginning, Q1, Q2 and Q...

    Sequential Circuits, Counters and Registers

29. GATE CS 2023MCQ2 marksMedium (estimate)

    GATE CS 2023, Q.44

    A Boolean digital circuit is composed using two 4-input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0–X7 are the inputs of the multiplexer...

    Combinational Circuits

30. GATE CS 2022MCQ1 markEasy (estimate)

    GATE CS 2022, Q.18

    Let $R_1$ and $R_2$ be two 4-bit registers that store numbers in 2's complement form. For the operation $R_1+R_2$, which one of the following values of $R_1$ and $R_2$ gives a...

    Number Representations and Computer Arithmetic

31. GATE CS 2022MCQ2 marksMedium (estimate)

    GATE CS 2022, Q.40

    Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S...

    Combinational Circuits

32. GATE CS 2021 Set 1MCQ1 markEasy (estimate)

    GATE CS 2021 Set 1, Q.16 (CS Q.6)

    Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?

    Number Representations and Computer Arithmetic

33. GATE CS 2021 Set 1NAT1 markEasy (estimate)

    GATE CS 2021 Set 1, Q.34 (CS Q.24)

    Consider the following representation of a number in IEEE 754 single-precision floating point format with a bias of 127. S: 1 E: 10000001 F: 11110000000000000000000 Here S, E an...

    Number Representations and Computer Arithmetic

34. GATE CS 2021 Set 1MCQ2 marksMedium (estimate)

    GATE CS 2021 Set 1, Q.38 (CS Q.28)

    Consider a 3-bit counter, designed using T flip-flops, as shown below: Synchronous 3-bit counter circuit designed using three T flip-flops with inputs Tp=R, Tq=P', and Tr=Q'. As...

    Sequential Circuits, Counters and Registers

35. GATE CS 2021 Set 1MSQ2 marksMedium (estimate)

    GATE CS 2021 Set 1, Q.52 (CS Q.42)

    Consider the following Boolean expression. $F=(X+Y+Z)(\overline{X}+Y)(\overline{Y}+Z)$ Which of the following Boolean expressions is/are equivalent to $\overline{F}$...

    Boolean Algebra and Logic Minimization

36. GATE CS 2021 Set 2MCQ1 markMedium (estimate)

    GATE CS 2021 Set 2, Q.14 (CS Q.4)

    The format of the single-precision floating-point representation of a real number as per the IEEE 754 standard is as follows: Sign bit: 1 bit, Exponent: 8 bits, Mantissa: 23 bit...

    Number Representations and Computer Arithmetic

37. GATE CS 2021 Set 2MCQ1 markMedium (estimate)

    GATE CS 2021 Set 2, Q.15 (CS Q.5)

    Which one of the following circuits implements the Boolean function given below? $f(x,y,z)=m_0+m_1+m_3+m_4+m_5+m_6$ where $m_i$ is the $i^{\text{th}}$ minterm.

    Combinational Circuits

38. GATE CS 2021 Set 2NAT1 markEasy (estimate)

    GATE CS 2021 Set 2, Q.28 (CS Q.18)

    If $x$ and $y$ are two decimal digits and $(0.1101{)}_2=(0.8xy5{)}_{10}$, the decimal value of $x+y$ is ______.

    Number Representations and Computer Arithmetic

39. GATE CS 2021 Set 2MCQ2 marksMedium (estimate)

    GATE CS 2021 Set 2, Q.38 (CS Q.28)

    Suppose we want to design a synchronous circuit that processes a string of 0's and 1's. Given a string, it produces another string by replacing the first 1 in any subsequence of...

    Sequential Circuits, Counters and Registers

40. GATE CS 2021 Set 2NAT2 marksMedium (estimate)

    GATE CS 2021 Set 2, Q.62 (CS Q.52)

    Consider a Boolean function $f(w,x,y,z)$ such that $\begin{array}{rl}f(w,0,0,z)& =1\\ f(1,x,1,z)& =x+z\\ f(w,1,y,z)& =wz+y\end{array}$ The number of lit...

    Combinational Circuits

41. GATE CS 2020NAT1 markEasy (estimate)

    GATE CS 2020, Q.29 (CS Q.19)

    A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will m...

    Combinational Circuits

42. GATE CS 2020NAT1 markEasy (estimate)

    GATE CS 2020, Q.30 (CS Q.20)

    If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of $m+n$ is _______.

    Combinational Circuits · Memory Hierarchy: Cache, Main Memory and Secondary Storage

43. GATE CS 2020MCQ2 marksEasy (estimate)

    GATE CS 2020, Q.38 (CS Q.28)

    Consider the Boolean function $z(a,b,c)$ represented by the logic circuit below. Logic circuit diagram with inputs a, b, c, an inverter on b, an AND gate combining not-b and c...

    Boolean Algebra and Logic Minimization · Combinational Circuits

44. GATE CS 2020MCQ2 marksMedium (estimate)

    GATE CS 2020, Q.39 (CS Q.29)

    Consider three registers R1, R2, and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation)...

    Number Representations and Computer Arithmetic

45. GATE CS 2019MCQ1 markEasy (estimate)

    GATE CS 2019, Q.14 (CS Q.4)

    In 16-bit 2's complement representation, the decimal number $-28$ is:

    Number Representations and Computer Arithmetic

46. GATE CS 2019MCQ1 markEasy (estimate)

    GATE CS 2019, Q.16 (CS Q.6)

    Which one of the following is NOT a valid identity?

    Boolean Algebra and Logic Minimization

47. GATE CS 2019MCQ1 markEasy (estimate)

    GATE CS 2019, Q.18 (CS Q.8)

    Consider $Z=X-Y$, where $X,Y$ and $Z$ are all in sign-magnitude form. $X$ and $Y$ are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would requi...

    Number Representations and Computer Arithmetic

48. GATE CS 2019MCQ2 marksMedium (estimate)

    GATE CS 2019, Q.40 (CS Q.30)

    Consider three 4-variable functions $f_1,f_2,$ and $f_3$, which are expressed in sum-of-minterms as…

    Combinational Circuits

49. GATE CS 2019NAT2 marksMedium (estimate)

    GATE CS 2019, Q.60 (CS Q.50)

    What is the minimum number of 2-input NOR gates required to implement a 4-variable function expressed in sum-of-minterms form as $f=\sum (0,2,5,7,8,10,13,15)$? Assume t...

    Boolean Algebra and Logic Minimization

50. GATE CS 2018MCQ1 markEasy (estimate)

    GATE CS 2018, Q.14 (CS Q.4)

    Let $\oplus$ and $\odot$ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?

    Boolean Algebra and Logic Minimization

51. GATE CS 2018NAT1 markEasy (estimate)

    GATE CS 2018, Q.32 (CS Q.22)

    Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. Sequential circuit with two positive edge-triggered D f...

    Sequential Circuits, Counters and Registers

52. GATE CS 2018MCQ2 marksEasy (estimate)

    GATE CS 2018, Q.43 (CS Q.33)

    Consider the unsigned 8-bit fixed point binary number representation below, $b_7{b}_6{b}_5{b}_4{b}_3.b_2{b}_1{b}_0$ where the position of the binary point...

    Number Representations and Computer Arithmetic

53. GATE CS 2018NAT2 marksMedium (estimate)

    GATE CS 2018, Q.59 (CS Q.49)

    Consider the minterm list form of a Boolean function $F$ given below. $F(P,Q,R,S)=\sum m(0,2,5,7,9,11)+d(3,8,10,12,14)$ Here, $m$ denotes a minterm and $d$ den...

    Boolean Algebra and Logic Minimization

54. GATE CS 2017 Set 1MCQ1 markEasy (estimate)

    GATE CS 2017 Set 1, Q.7 (CS Q.7)

    The $n$-bit fixed-point representation of an unsigned real number $X$ uses $f$ bits for the fraction part. Let $i=n-f$. The range of decimal values for $X$ in this represent...

    Number Representations and Computer Arithmetic

55. GATE CS 2017 Set 1NAT1 markMedium (estimate)

    GATE CS 2017 Set 1, Q.21 (CS Q.21)

    Consider the Karnaugh map given below, where X represents "don't care" and blank represents 0. 4 by 4 Karnaugh map for a 4-variable Boolean logic function with row variables dc...

    Boolean Algebra and Logic Minimization · Combinational Circuits

56. GATE CS 2017 Set 1MCQ2 marksEasy (estimate)

    GATE CS 2017 Set 1, Q.33 (CS Q.33)

    Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-fl...

    Sequential Circuits, Counters and Registers

57. GATE CS 2017 Set 2MCQ1 markEasy (estimate)

    GATE CS 2017 Set 2, Q.1 (CS Q.1)

    The representation of the value of a 16-bit unsigned integer $Y$ in hexadecimal number system is $\text{BCA9}$. The representation of the value of $Y$ in octal number system is

    Number Representations and Computer Arithmetic

58. GATE CS 2017 Set 2MCQ1 markMedium (estimate)

    GATE CS 2017 Set 2, Q.12 (CS Q.12)

    Given the following binary number in 32-bit (single precision) IEEE-754 format: 00111110011011010000000000000000 The decimal value closest to this floating-point number is

    Number Representations and Computer Arithmetic

59. GATE CS 2017 Set 2NAT1 markEasy (estimate)

    GATE CS 2017 Set 2, Q.24 (CS Q.24)

    Consider a quadratic equation $x^2-13x+36=0$ with coefficients in a base $b$. The solutions of this equation in the same base $b$ are $x=5$ and $x=6$. Then $b=$

    Number Representations and Computer Arithmetic

60. GATE CS 2017 Set 2MCQ2 marksMedium (estimate)

    GATE CS 2017 Set 2, Q.27 (CS Q.27)

    If $w,x,y,z$ are Boolean variables, then which one of the following is INCORRECT?

    Boolean Algebra and Logic Minimization

61. GATE CS 2017 Set 2MCQ2 marksMedium (estimate)

    GATE CS 2017 Set 2, Q.28 (CS Q.28)

    Given $f(w,x,y,z)=\sum m(0,1,2,3,7,8,10)+\sum d(5,6,11,15)$, where $d$ represents the don’t-care condition in Karnaugh maps. Which of the following is a minimum product-of-s...

    Boolean Algebra and Logic Minimization

62. GATE CS 2017 Set 2MCQ2 marksMedium (estimate)

    GATE CS 2017 Set 2, Q.42 (CS Q.42)

    The next state table of a 2-bit saturating up-counter is given below. | $Q_1$ | $Q_0$ | $Q_1^{+}$ | $Q_0^{+}$ | | :-: | :-: | :-: | :-: | | 0 | 0 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0...

    Sequential Circuits, Counters and Registers

63. GATE CS 2016 Set 1MCQ1 markEasy (estimate)

    GATE CS 2016 Set 1, Q.16 (CS Q.6)

    Consider the Boolean operator $\#$ with the following properties: $x\#0=x$, $x\#1=\bar{x}$, $x\#x=0$ and $x\#\bar{x}=1$. Then $x\#y$ is equivalent to

    Boolean Algebra and Logic Minimization

64. GATE CS 2016 Set 1NAT1 markEasy (estimate)

    GATE CS 2016 Set 1, Q.17 (CS Q.7)

    The 16-bit 2's complement representation of an integer is 1111 1111 1111 0101; its decimal representation is _____.

    Number Representations and Computer Arithmetic

65. GATE CS 2016 Set 1NAT1 markMedium (estimate)

    GATE CS 2016 Set 1, Q.18 (CS Q.8)

    We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is _____.

    Sequential Circuits, Counters and Registers

66. GATE CS 2016 Set 1MCQ2 marksMedium (estimate)

    GATE CS 2016 Set 1, Q.40 (CS Q.30)

    Consider the two cascaded 2-to-1 multiplexers as shown in the figure. Logic circuit diagram of two cascaded 2-to-1 multiplexers. The first multiplexer has select input P, data i...

    Combinational Circuits

67. GATE CS 2016 Set 1MCQ2 marksMedium (estimate)

    GATE CS 2016 Set 1, Q.43 (CS Q.33)

    Consider a carry lookahead adder for adding two $n$-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

    Number Representations and Computer Arithmetic

68. GATE CS 2016 Set 2NAT1 markMedium (estimate)

    GATE CS 2016 Set 2, Q.17 (CS Q.7)

    Consider an eight-bit ripple-carry adder for computing the sum of $A$ and $B$, where $A$ and $B$ are integers represented in 2's complement form. If the decimal value of $A$ is...

    Number Representations and Computer Arithmetic

69. GATE CS 2016 Set 2MCQ1 markEasy (estimate)

    GATE CS 2016 Set 2, Q.18 (CS Q.8)

    Let $x_1\oplus x_2\oplus x_3\oplus x_4=0$ where $x_1,x_2,x_3,x_4$ are Boolean variables, and $\oplus$ is the XOR operator. Which one of the following must always be TRUE?

    Boolean Algebra and Logic Minimization

70. GATE CS 2016 Set 2NAT1 markEasy (estimate)

    GATE CS 2016 Set 2, Q.19 (CS Q.9)

    Let $X$ be the number of distinct 16-bit integers in 2's complement representation. Let $Y$ be the number of distinct 16-bit integers in sign magnitude representation. Then…

    Number Representations and Computer Arithmetic

71. GATE CS 2015 Set 1MCQ1 markEasy (estimate)

    GATE CS 2015 Set 1, Q.30 (CS Q.20)

    Consider a 4-bit Johnson counter with an initial value of $0000$. The counting sequence of this counter is:

    Sequential Circuits, Counters and Registers

72. GATE CS 2015 Set 1MCQ2 marksEasy (estimate)

    GATE CS 2015 Set 1, Q.38 (CS Q.28)

    The binary operator $\ne$ is defined by the following truth table: | $p$ | $q$ | $p\ne q$ | | :---: | :---: | :---: | | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 | Wh...

    Boolean Algebra and Logic Minimization

73. GATE CS 2015 Set 1MCQ2 marksMedium (estimate)

    GATE CS 2015 Set 1, Q.47 (CS Q.37)

    A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs...

    Sequential Circuits, Counters and Registers

74. GATE CS 2015 Set 1MCQ2 marksMedium (estimate)

    GATE CS 2015 Set 1, Q.49 (CS Q.39)

    Consider the operations: $f(X,Y,Z)=X^{\prime }YZ+X{Y}^{\prime }+Y^{\prime }{Z}^{\prime }\text{and}g(X,Y,Z)=X^{\prime }YZ+X^{\prime }Y{Z}^{\prime }+XY.$ Which one of the following is correct?

    Boolean Algebra and Logic Minimization

75. GATE CS 2015 Set 2NAT1 markEasy (estimate)

    GATE CS 2015 Set 2, Q.17 (CS Q.7)

    The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence $(0,0,1,1,2,2,3,3,0,0,\dots )$ is _____.

    Sequential Circuits, Counters and Registers

76. GATE CS 2015 Set 2NAT2 marksMedium (estimate)

    GATE CS 2015 Set 2, Q.47 (CS Q.37)

    The number of min-terms after minimizing the following Boolean expression is _____. $[D^{\prime }+A{B}^{\prime }+A^{\prime }C+A{C}^{\prime }D+A^{\prime }{C}^{\prime }D{]}^{\prime }$

    Boolean Algebra and Logic Minimization

77. GATE CS 2015 Set 2NAT2 marksMedium (estimate)

    GATE CS 2015 Set 2, Q.58 (CS Q.48)

    A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AN...

    Combinational Circuits

78. GATE CS 2015 Set 3MCQ1 markEasy (estimate)

    GATE CS 2015 Set 3, Q.12 (CS Q.2)

    Let $\#$ be a binary operator defined as $X\#Y=X^{\prime }+Y^{\prime }$ where $X$ and $Y$ are Boolean variables. Consider the following two statements. (S1)…

    Boolean Algebra and Logic Minimization

79. GATE CS 2015 Set 3NAT2 marksMedium (estimate)

    GATE CS 2015 Set 3, Q.45 (CS Q.35)

    Consider the equation $(43{)}_x=(y3{)}_8$ where $x$ and $y$ are unknown. The number of possible solutions is _____.

    Number Representations and Computer Arithmetic

80. GATE CS 2015 Set 3NAT2 marksMedium (estimate)

    GATE CS 2015 Set 3, Q.53 (CS Q.43)

    The total number of prime implicants of the function $f(w,x,y,z)=\sum (0,2,4,5,6,10)$ is _____.

    Boolean Algebra and Logic Minimization

81. GATE CS 2015 Set 3MCQ2 marksEasy (estimate)

    GATE CS 2015 Set 3, Q.54 (CS Q.44)

    Given the function $F=P^{\prime }+QR$, where $F$ is a function in three Boolean variables $P,Q$ and $R$ and $P^{\prime }=\neg P$, consider the following statements. (S1)…

    Boolean Algebra and Logic Minimization

82. GATE CS 2014 Set 1MCQ1 markEasy (estimate)

    GATE CS 2014 Set 1, Q.17 (CS Q.7)

    Consider the following Boolean expression for $F$: $F(P,Q,R,S)=PQ+\bar{P}QR+\bar{P}Q\bar{R}S$ The minimal sum-of-products form of $F$ is

    Boolean Algebra and Logic Minimization

83. GATE CS 2014 Set 1NAT1 markEasy (estimate)

    GATE CS 2014 Set 1, Q.18 (CS Q.8)

    The base (or radix) of the number system such that the following equation holds is____________. $\frac{312}{20}=13.1$

    Number Representations and Computer Arithmetic

84. GATE CS 2014 Set 1MCQ2 marksMedium (estimate)

    GATE CS 2014 Set 1, Q.55 (CS Q.45)

    Consider the 4-to-1 multiplexer with two select lines $P$ and $Q$ given below. 4-to-1 Multiplexer with inputs 0, 1, R, R-bar, select lines P, Q, and output F The minimal sum-of-...

    Combinational Circuits

85. GATE CS 2014 Set 2MCQ1 markEasy (estimate)

    GATE CS 2014 Set 2, Q.16 (CS Q.6)

    The dual of a Boolean function $F(x_1,x_2,\dots ,x_n,+,\cdot {,}^{\prime })$, written as $F^D$, is the same expression as that of $F$ with $+$ and $\cdot$ swapped. $F$ is said to be se...

    Boolean Algebra and Logic Minimization

86. GATE CS 2014 Set 2MCQ1 markEasy (estimate)

    GATE CS 2014 Set 2, Q.17 (CS Q.7)

    Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n$-to-$2^n$ bit decoder. This circuit is equivalent to a

    Sequential Circuits, Counters and Registers

87. GATE CS 2014 Set 2NAT1 markMedium (estimate)

    GATE CS 2014 Set 2, Q.18 (CS Q.8)

    Consider the equation $(123{)}_5=(x8{)}_y$ with $x$ and $y$ as unknown. The number of possible solutions is _____.

    Number Representations and Computer Arithmetic

88. GATE CS 2014 Set 2MCQ2 marksEasy (estimate)

    GATE CS 2014 Set 2, Q.55 (CS Q.45)

    The value of a float type variable is represented using the single-precision 32-bit floating point format of IEEE-754 standard that uses 1 bit for sign, 8 bits for biased expone...

    Number Representations and Computer Arithmetic

89. GATE CS 2014 Set 3MCQ1 markEasy (estimate)

    GATE CS 2014 Set 3, Q.17 (CS Q.7)

    Consider the following minterm expression for $F$: $F(P,Q,R,S)=\sum m(0,2,5,7,8,10,13,15)$ The minterms 2, 7, 8 and 13 are 'do not care' terms. The minimal sum-of-...

    Boolean Algebra and Logic Minimization

90. GATE CS 2014 Set 3MCQ1 markEasy (estimate)

    GATE CS 2014 Set 3, Q.18 (CS Q.8)

    Consider the following combinational function block involving four Boolean variables $x,y,a,b$ where $x,a,b$ are inputs and $y$ is the output. f (x, y, a, b) { if (x is 1)...

    Combinational Circuits

91. GATE CS 2014 Set 3MCQ2 marksMedium (estimate)

    GATE CS 2014 Set 3, Q.55 (CS Q.45)

    Synchronous sequential circuit built using three JK flip-flops Q2, Q1, and Q0 with feedback logic Synchronous sequential circuit using JK flip-flops The above synchronous sequen...

    Sequential Circuits, Counters and Registers

92. GATE CS 2014 Set 3MCQ2 marksEasy (estimate)

    GATE CS 2014 Set 3, Q.65 (CS Q.55)

    Let $\oplus$ denote the Exclusive OR (XOR) operation. Let '1' and '0' denote the binary constants. Consider the following Boolean expression for $F$ over two variables $P$ and…

    Boolean Algebra and Logic Minimization

93. GATE CS 2013MCQ1 markEasy (estimate)

    GATE CS 2013, Q.4 (CS Q.4)

    The smallest integer that can be represented by an 8-bit number in 2’s complement form is

    Number Representations and Computer Arithmetic

94. GATE CS 2013MCQ1 markEasy (estimate)

    GATE CS 2013, Q.5 (CS Q.5)

    In the following truth table, $V=1$ if and only if the input is valid. What function does the truth table represent? D0 D1 D2 D3 X0 X1 V 0 0 0 0 x x 0 1 0 0 0 0 0 1 x 1 0 0 0...

    Combinational Circuits

95. GATE CS 2013MCQ1 markEasy (estimate)

    GATE CS 2013, Q.21 (CS Q.21)

    Which one of the following expressions does NOT represent exclusive NOR of $x$ and $y$?

    Boolean Algebra and Logic Minimization

96. GATE CS 2012MCQ1 markEasy (estimate)

    GATE CS 2012, Q.6 (CS Q.6)

    The truth table $\begin{array}{ccc}X& Y& f(X,Y)\\ 0& 0& 0\\ 0& 1& 0\\ 1& 0& 1\\ 1& 1& 1\end{array}$ represents the Boolean function

    Boolean Algebra and Logic Minimization

97. GATE CS 2012MCQ1 markEasy (estimate)

    GATE CS 2012, Q.7 (CS Q.7)

    The decimal value 0.5 in IEEE single precision floating point representation has

    Number Representations and Computer Arithmetic

98. GATE CS 2012MCQ1 markEasy (estimate)

    GATE CS 2012, Q.19 (CS Q.19)

    The amount of ROM needed to implement a 4 bit multiplier is

    Combinational Circuits · Combinational Circuits

99. GATE CS 2012MCQ2 marksMedium (estimate)

    GATE CS 2012, Q.30 (CS Q.30)

    What is the minimal form of the Karnaugh map shown below? Assume that $X$ denotes a don't care term. Four-variable Karnaugh map for variables a, b, c, d with specified 1s and do...

    Boolean Algebra and Logic Minimization · Boolean Algebra and Logic Minimization

100. GATE CS 2011MCQ1 markMedium (estimate)

     GATE CS 2011, Q.13 (CS Q.13)

     Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?

     Combinational Circuits

101. GATE CS 2011MCQ1 markEasy (estimate)

     GATE CS 2011, Q.14 (CS Q.14)

     The simplified SOP (Sum of Product) form of the Boolean expression $(P+\overline{Q}+\overline{R})\cdot (P+\overline{Q}+R)\cdot (P+Q+\overline{R})$ is

     Boolean Algebra and Logic Minimization

102. GATE CS 2011MCQ1 markEasy (estimate)

     GATE CS 2011, Q.15 (CS Q.15)

     The minimum number of D flip-flops needed to design a mod-258 counter is

     Sequential Circuits, Counters and Registers

103. GATE CS 2011MCQ2 marksMedium (estimate)

     GATE CS 2011, Q.50 (CS Q.50)

     If at some instance prior to the occurrence of the clock edge, $P,Q$ and $R$ have a value 0, 1 and 0 respectively, what shall be the value of $PQR$ after the clock edge?

     Sequential Circuits, Counters and Registers

104. GATE CS 2011MCQ2 marksMedium (estimate)

     GATE CS 2011, Q.51 (CS Q.51)

     If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by $PQR$ generated by the counter?

     Sequential Circuits, Counters and Registers