GATE CS 2011 Q.50 (CS Q.50): Sequential Circuits, Counters and Registers

Common data questions

Common Data for Questions 50 and 51:

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

Synchronous counter circuit with three D flip-flops P, Q, R, NOR gate generating D of Q from P and R, and AND gate generating D of R from Q and R-bar

If at some instance prior to the occurrence of the clock edge, $P, Q$ and $R$ have a value 0, 1 and 0 respectively, what shall be the value of $PQR$ after the clock edge?

000

001

010

011

Official answer and solution

Official answer: D
From: Official GATE 2011 answer key

Solution

Derive the next-state Boolean expressions for the three D flip-flops from the circuit schematic.

From the circuit diagram:

The input $D_P$ connects to the output $R$ of flip-flop R: $D_P = R$ .
The NOR gate receives inputs $P$ and $R$ , feeding $D_Q$ : $D_Q = \overline{P + R}$ .
The AND gate receives input $Q$ and inverted output $\overline{R}$ of flip-flop R, feeding $D_R$ : $D_R = Q \cdot \overline{R}$ .

Given initial state prior to clock edge: $P = 0, Q = 1, R = 0$ .

Evaluate the flip-flop inputs:

$D_P = R = 0$
$D_Q = \overline{0 + 0} = 1$
$D_R = Q \cdot \overline{R} = 1 \cdot \overline{0} = 1 \cdot 1 = 1$

After the clock edge, the next state $(P^+, Q^+, R^+) = (D_P, D_Q, D_R) = (0, 1, 1) = 011$ .

Final answer

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2011 Computer Science and Information Technology (CS)
Question: 50 of 65, printed as CS Q.50
Section: Computer Science and Information Technology

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