Question

Consider a carry lookahead adder for adding two nn-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is

Choose one option
Official answer and solution
Official answer
B
From
Official GATE 2016 answer key

Solution

Evaluate tree depth required to compute prefix carries when gate fan-in is bounded by two.

In a Carry Lookahead Adder (CLA), carry generation terms Gi=AiBiG_i = A_i B_i and propagation terms Pi=Ai⊕BiP_i = A_i \oplus B_i are computed in O(1)O(1) time.

The ii-th carry CiC_i is expressed as:

Ci=Gi+PiCi−1=Gi+PiGi−1+PiPi−1Gi−2+⋯+PiPi−1…P0C−1C_i = G_i + P_i C_{i-1} = G_i + P_i G_{i-1} + P_i P_{i-1} G_{i-2} + \dots + P_i P_{i-1} \dots P_0 C_{-1}

For an nn-bit adder, this expression involves an nn-input OR gate and AND gates with fan-in up to nn.

When gate fan-in is restricted to at most 2, an nn-input Boolean function must be implemented using a binary tree of 2-input logic gates.
The height (depth) of a balanced binary tree with nn inputs is ⌈log⁡2n⌉\lceil \log_2 n \rceil.

Using parallel prefix adder architectures (such as Brent-Kung or Kogge-Stone), prefix carries can be computed in Θ(log⁡n)\Theta(\log n) gate levels.
Therefore, the addition time is Θ(log⁡n)\Theta(\log n).

Final answer

B

Common trap

Assuming CLA addition takes Θ(1)\Theta(1) time, forgetting that Θ(1)\Theta(1) requires unbounded gate fan-in, which is physically prohibited by the fan-in ≤2\le 2 constraint.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2016 Computer Science and Information Technology (CS) Session 1
Question
43 of 65, printed as CS Q.33
Section
Computer Science and Information Technology

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