Sequential Circuits, Counters and Registers: GATE CS previous year questions (Digital Logic)

GATE CS 2026 Set 1MCQ2 marksMedium (estimate)
GATE CS 2026 Set 1, Q.37
Consider a 2-bit saturating up/down counter that performs the saturating up count when the input $P$ is 0, and the saturating down count when $P$ is 1. The Next State table of t...
Sequential Circuits, Counters and Registers
GATE CS 2025 Set 1NAT2 marksMedium (estimate)
GATE CS 2025 Set 1, Q.59
Consider a finite state machine (FSM) with one input $X$ and one output $f$ , represented by the given state transition table. The minimum number of states required to realize th...
Sequential Circuits, Counters and Registers
GATE CS 2025 Set 1NAT2 marksMedium (estimate)
GATE CS 2025 Set 1, Q.60
Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go...
Sequential Circuits, Counters and Registers
GATE CS 2025 Set 2NAT1 markEasy (estimate)
GATE CS 2025 Set 2, Q.34
In a 4-bit ripple counter, if the period of the waveform at the last flip-flop is 64 microseconds, then the frequency of the ripple counter in kHz is ________. (Answer in integer)
Sequential Circuits, Counters and Registers
GATE CS 2023MCQ1 markMedium (estimate)
GATE CS 2023, Q.21
The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. A 2-input multiplexer with inputs 0 and 1, select line S, and output Q connect...
Combinational Circuits · Sequential Circuits, Counters and Registers
GATE CS 2023MCQ2 marksMedium (estimate)
GATE CS 2023, Q.43
Consider a sequential digital circuit consisting of T flip-flops and D flip-flops as shown in the figure. CLKIN is the clock input to the circuit. At the beginning, Q1, Q2 and Q...
Sequential Circuits, Counters and Registers
GATE CS 2021 Set 1MCQ2 marksMedium (estimate)
GATE CS 2021 Set 1, Q.38 (CS Q.28)
Consider a 3-bit counter, designed using T flip-flops, as shown below: Synchronous 3-bit counter circuit designed using three T flip-flops with inputs Tp=R, Tq=P', and Tr=Q'. As...
Sequential Circuits, Counters and Registers
GATE CS 2021 Set 2MCQ2 marksMedium (estimate)
GATE CS 2021 Set 2, Q.38 (CS Q.28)
Suppose we want to design a synchronous circuit that processes a string of 0's and 1's. Given a string, it produces another string by replacing the first 1 in any subsequence of...
Sequential Circuits, Counters and Registers
GATE CS 2018NAT1 markEasy (estimate)
GATE CS 2018, Q.32 (CS Q.22)
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops. Sequential circuit with two positive edge-triggered D f...
Sequential Circuits, Counters and Registers
GATE CS 2017 Set 1MCQ2 marksEasy (estimate)
GATE CS 2017 Set 1, Q.33 (CS Q.33)
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-fl...
Sequential Circuits, Counters and Registers
GATE CS 2017 Set 2MCQ2 marksMedium (estimate)
GATE CS 2017 Set 2, Q.42 (CS Q.42)
The next state table of a 2-bit saturating up-counter is given below. | $Q_{1}$ | $Q_{0}$ | $Q_{1}^{+}$ | $Q_{0}^{+}$ | | :-: | :-: | :-: | :-: | | 0 | 0 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0...
Sequential Circuits, Counters and Registers
GATE CS 2016 Set 1NAT1 markMedium (estimate)
GATE CS 2016 Set 1, Q.18 (CS Q.8)
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is _____.
Sequential Circuits, Counters and Registers
GATE CS 2015 Set 1MCQ1 markEasy (estimate)
GATE CS 2015 Set 1, Q.30 (CS Q.20)
Consider a 4-bit Johnson counter with an initial value of $0000$ . The counting sequence of this counter is:
Sequential Circuits, Counters and Registers
GATE CS 2015 Set 1MCQ2 marksMedium (estimate)
GATE CS 2015 Set 1, Q.47 (CS Q.37)
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs...
Sequential Circuits, Counters and Registers
GATE CS 2015 Set 2NAT1 markEasy (estimate)
GATE CS 2015 Set 2, Q.17 (CS Q.7)
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \dots)$ is _____.
Sequential Circuits, Counters and Registers
GATE CS 2014 Set 2MCQ1 markEasy (estimate)
GATE CS 2014 Set 2, Q.17 (CS Q.7)
Let $k = 2^{n}$ . A circuit is built by giving the output of an $n$ -bit binary counter as input to an $n$ -to- $2^{n}$ bit decoder. This circuit is equivalent to a
Sequential Circuits, Counters and Registers
GATE CS 2014 Set 3MCQ2 marksMedium (estimate)
GATE CS 2014 Set 3, Q.55 (CS Q.45)
Synchronous sequential circuit built using three JK flip-flops Q2, Q1, and Q0 with feedback logic Synchronous sequential circuit using JK flip-flops The above synchronous sequen...
Sequential Circuits, Counters and Registers
GATE CS 2011MCQ1 markEasy (estimate)
GATE CS 2011, Q.15 (CS Q.15)
The minimum number of D flip-flops needed to design a mod-258 counter is
Sequential Circuits, Counters and Registers
GATE CS 2011MCQ2 marksMedium (estimate)
GATE CS 2011, Q.50 (CS Q.50)
If at some instance prior to the occurrence of the clock edge, $P, Q$ and $R$ have a value 0, 1 and 0 respectively, what shall be the value of $P QR$ after the clock edge?
Sequential Circuits, Counters and Registers
GATE CS 2011MCQ2 marksMedium (estimate)
GATE CS 2011, Q.51 (CS Q.51)
If all the flip-flops were reset to 0 at power on, what is the total number of distinct outputs (states) represented by $P QR$ generated by the counter?
Sequential Circuits, Counters and Registers

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