Question 21

For a 2-to-1 multiplexer with select input $S$, data inputs $I_0, I_1$, and output $Q$:

From the circuit diagram, input $0$ is connected back to the output ($I_0 = Q$), and input $1$ is connected to an external input, say $D$ ($I_1 = D$):

• When $S = 1$: $Q_{next} = D$, meaning the circuit is transparent and passes the input $D$ to output $Q$.
• When $S = 0$: $Q_{next} = Q$, meaning the circuit latches and holds its current state.

Because this operation is level-sensitive (acting on the level of $S$, not on clock edges), it functions precisely as a D Latch (with $S$ acting as the enable/clock input).