Question

A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J=K=1J = K = 1 is the toggle mode and J=K=0J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.

Choose one option
Official answer and solution
Official answer
A
From
Official GATE 2015 answer key

Solution

Trace the cycle-by-cycle state transitions of the coupled D and JK flip-flops from the initial state.

Flip-flop connections:

  • Din=QJKD_{\text{in}} = Q_{JK}
  • J=K=QDJ = K = Q_D (toggle mode when QD=1Q_D = 1; hold mode when QD=0Q_D = 0)

Initial state at t=0t = 0: QD=1,QJK=0Q_D = 1, Q_{JK} = 0.

Tracing successive clock cycles:

  • Cycle 1:
    Inputs before clock: D=0D = 0, J=K=1J = K = 1.
    Next states: QD+=0Q_D^+ = 0, QJK+=QJK‾=0‾=1Q_{JK}^+ = \overline{Q_{JK}} = \overline{0} = 1.
    Output: QJK=1Q_{JK} = 1.

  • Cycle 2:
    Inputs before clock: D=1D = 1, J=K=0J = K = 0.
    Next states: QD+=1Q_D^+ = 1, QJK+=QJK=1Q_{JK}^+ = Q_{JK} = 1 (holds).
    Output: QJK=1Q_{JK} = 1.

  • Cycle 3:
    Inputs before clock: D=1D = 1, J=K=1J = K = 1.
    Next states: QD+=1Q_D^+ = 1, QJK+=QJK‾=1‾=0Q_{JK}^+ = \overline{Q_{JK}} = \overline{1} = 0.
    Output: QJK=0Q_{JK} = 0.

  • Cycle 4:
    Inputs before clock: D=0D = 0, J=K=1J = K = 1.
    State is (QD=1,QJK=0)(Q_D = 1, Q_{JK} = 0), exactly repeating Cycle 1.

The sequence of bits generated at QJKQ_{JK} starting from the initial state is:

0,1,1,0,1,1,0,…0, 1, 1, 0, 1, 1, 0, \dots

This matches option A.

Final answer

A

Common trap

Omitting the initial state bit 0 from the printed output sequence.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2015 Computer Science and Information Technology (CS) Session 1
Question
47 of 65, printed as CS Q.37
Section
Computer Science and Information Technology

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