Question
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flip-flop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that is the toggle mode and is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
Official answer and solution
- Official answer
- A
- From
- Official GATE 2015 answer key
Solution
Trace the cycle-by-cycle state transitions of the coupled D and JK flip-flops from the initial state.
Flip-flop connections:
- (toggle mode when ; hold mode when )
Initial state at : .
Tracing successive clock cycles:
-
Cycle 1:
Inputs before clock: , .
Next states: , .
Output: . -
Cycle 2:
Inputs before clock: , .
Next states: , (holds).
Output: . -
Cycle 3:
Inputs before clock: , .
Next states: , .
Output: . -
Cycle 4:
Inputs before clock: , .
State is , exactly repeating Cycle 1.
The sequence of bits generated at starting from the initial state is:
This matches option A.
A
Omitting the initial state bit 0 from the printed output sequence.
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2015 Computer Science and Information Technology (CS) Session 1
- Question
- 47 of 65, printed as CS Q.37
- Section
- Computer Science and Information Technology
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