Question

Let R1R_1 and R2R_2 be two 4-bit registers that store numbers in 2's complement form. For the operation R1+R2R_1 + R_2, which one of the following values of R1R_1 and R2R_2 gives an arithmetic overflow?

Choose one option
Official answer and solution
Official answer
B
From
Official GATE 2022 answer key

Solution

Evaluate the 4-bit two's complement values and detect overflow when the sum of two numbers of the same sign produces a result of the opposite sign.

In 4-bit 2's complement representation, the range of representable integers is [−23,23−1]=[−8,+7][-2^3, 2^3 - 1] = [-8, +7].

Let us evaluate each option:

  • (A) R1=10112=−5R_1 = 1011_2 = -5, R2=11102=−2R_2 = 1110_2 = -2. Sum: −5+(−2)=−7-5 + (-2) = -7. Since −7∈[−8,+7]-7 \in [-8, +7], no overflow occurs.
  • (B) R1=11002=−4R_1 = 1100_2 = -4, R2=10102=−6R_2 = 1010_2 = -6. Sum: −4+(−6)=−10-4 + (-6) = -10. Since −10<−8-10 < -8, the true sum cannot be represented in 4 bits. In binary addition: 11002+10102=(1)011021100_2 + 1010_2 = (1)0110_2. The result has sign bit 0 (representing +6+6), indicating negative overflow.
  • (C) R1=00112=+3R_1 = 0011_2 = +3, R2=01002=+4R_2 = 0100_2 = +4. Sum: +3+(+4)=+7∈[−8,+7]+3 + (+4) = +7 \in [-8, +7], no overflow.
  • (D) R1=10012=−7R_1 = 1001_2 = -7, R2=11112=−1R_2 = 1111_2 = -1. Sum: −7+(−1)=−8∈[−8,+7]-7 + (-1) = -8 \in [-8, +7], no overflow.

Thus, only Option (B) results in arithmetic overflow.

Final answer

Option (B)

Common trap

Confusing the end carry out of the MSB with an arithmetic overflow condition.

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper
GATE 2022 Computer Science and Information Technology (CS)
Question
18 of 65
Section
Computer Science and Information Technology

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