Combinational Circuits: GATE CS previous year questions (Digital Logic)

GATE CS 2026 Set 2NAT2 marksEasy (estimate)
GATE CS 2026 Set 2, Q.59
Consider the digital circuit shown below with two input lines A and B, two select lines S0 and S1, and an output line Y. The blocks Q and M represent active high 2:4 decoder and...
Combinational Circuits
GATE CS 2025 Set 2MSQ1 markEasy (estimate)
GATE CS 2025 Set 2, Q.31
Consider the following logic circuit diagram. Logic circuit with inputs Y and X feeding three branches into a 3-input OR gate with output F: top branch is a 2-input NAND gate of...
Boolean Algebra and Logic Minimization · Combinational Circuits
GATE CS 2024 Set 1MSQ1 markMedium (estimate)
GATE CS 2024 Set 1, Q.28
Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of th...
Combinational Circuits
GATE CS 2024 Set 1NAT2 marksEasy (estimate)
GATE CS 2024 Set 1, Q.64
Consider a digital logic circuit consisting of three 2-to-1 multiplexers M1, M2, and M3 as shown below. X1 and X2 are inputs of M1. X3 and X4 are inputs of M2. A, B, and C are s...
Combinational Circuits
GATE CS 2024 Set 2MSQ2 marksEasy (estimate)
GATE CS 2024 Set 2, Q.50
Consider 4-variable functions $f 1, f 2, f 3, f 4$ expressed in sum-of-minterms form as given below. $f 1 = \sum (0, 2, 3, 5, 7, 8, 11, 13)$ $f 2 = \sum (1, 3, 5, 7, 11, 13, 15)$ …
Combinational Circuits · Boolean Algebra and Logic Minimization
GATE CS 2023MCQ1 markMedium (estimate)
GATE CS 2023, Q.21
The output of a 2-input multiplexer is connected back to one of its inputs as shown in the figure. A 2-input multiplexer with inputs 0 and 1, select line S, and output Q connect...
Combinational Circuits · Sequential Circuits, Counters and Registers
GATE CS 2023MCQ2 marksMedium (estimate)
GATE CS 2023, Q.44
A Boolean digital circuit is composed using two 4-input multiplexers (M1 and M2) and one 2-input multiplexer (M3) as shown in the figure. X0–X7 are the inputs of the multiplexer...
Combinational Circuits
GATE CS 2022MCQ2 marksMedium (estimate)
GATE CS 2022, Q.40
Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S...
Combinational Circuits
GATE CS 2021 Set 2MCQ1 markMedium (estimate)
GATE CS 2021 Set 2, Q.15 (CS Q.5)
Which one of the following circuits implements the Boolean function given below? $f (x, y, z) = m_{0} + m_{1} + m_{3} + m_{4} + m_{5} + m_{6}$ where $m_{i}$ is the $i^{th}$ minterm.
Combinational Circuits
GATE CS 2021 Set 2NAT2 marksMedium (estimate)
GATE CS 2021 Set 2, Q.62 (CS Q.52)
Consider a Boolean function $f (w, x, y, z)$ such that $f (w, 0, 0, z) f (1, x, 1, z) f (w, 1, y, z) = 1 = x + z = w z + y$ The number of lit...
Combinational Circuits
GATE CS 2020NAT1 markEasy (estimate)
GATE CS 2020, Q.29 (CS Q.19)
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will m...
Combinational Circuits
GATE CS 2020NAT1 markEasy (estimate)
GATE CS 2020, Q.30 (CS Q.20)
If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of $m + n$ is _______.
Combinational Circuits · Memory Hierarchy: Cache, Main Memory and Secondary Storage
GATE CS 2020MCQ2 marksEasy (estimate)
GATE CS 2020, Q.38 (CS Q.28)
Consider the Boolean function $z (a, b, c)$ represented by the logic circuit below. Logic circuit diagram with inputs a, b, c, an inverter on b, an AND gate combining not-b and c...
Boolean Algebra and Logic Minimization · Combinational Circuits
GATE CS 2019MCQ2 marksMedium (estimate)
GATE CS 2019, Q.40 (CS Q.30)
Consider three 4-variable functions $f_{1}, f_{2},$ and $f_{3}$ , which are expressed in sum-of-minterms as…
Combinational Circuits
GATE CS 2017 Set 1NAT1 markMedium (estimate)
GATE CS 2017 Set 1, Q.21 (CS Q.21)
Consider the Karnaugh map given below, where X represents "don't care" and blank represents 0. 4 by 4 Karnaugh map for a 4-variable Boolean logic function with row variables dc...
Boolean Algebra and Logic Minimization · Combinational Circuits
GATE CS 2016 Set 1MCQ2 marksMedium (estimate)
GATE CS 2016 Set 1, Q.40 (CS Q.30)
Consider the two cascaded 2-to-1 multiplexers as shown in the figure. Logic circuit diagram of two cascaded 2-to-1 multiplexers. The first multiplexer has select input P, data i...
Combinational Circuits
GATE CS 2015 Set 2NAT2 marksMedium (estimate)
GATE CS 2015 Set 2, Q.58 (CS Q.48)
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AN...
Combinational Circuits
GATE CS 2014 Set 1MCQ2 marksMedium (estimate)
GATE CS 2014 Set 1, Q.55 (CS Q.45)
Consider the 4-to-1 multiplexer with two select lines $P$ and $Q$ given below. 4-to-1 Multiplexer with inputs 0, 1, R, R-bar, select lines P, Q, and output F The minimal sum-of-...
Combinational Circuits
GATE CS 2014 Set 3MCQ1 markEasy (estimate)
GATE CS 2014 Set 3, Q.18 (CS Q.8)
Consider the following combinational function block involving four Boolean variables $x, y, a, b$ where $x, a, b$ are inputs and $y$ is the output. f (x, y, a, b) { if (x is 1)...
Combinational Circuits
GATE CS 2013MCQ1 markEasy (estimate)
GATE CS 2013, Q.5 (CS Q.5)
In the following truth table, $V = 1$ if and only if the input is valid. What function does the truth table represent? D0 D1 D2 D3 X0 X1 V 0 0 0 0 x x 0 1 0 0 0 0 0 1 x 1 0 0 0...
Combinational Circuits
GATE CS 2012MCQ1 markEasy (estimate)
GATE CS 2012, Q.19 (CS Q.19)
The amount of ROM needed to implement a 4 bit multiplier is
Combinational Circuits · Combinational Circuits
GATE CS 2011MCQ1 markMedium (estimate)
GATE CS 2011, Q.13 (CS Q.13)
Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?
Combinational Circuits

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