Latches and Flip-Flops

Latches and flip-flops are bistable memory elements. A latch is level-sensitive: while the enable is asserted it follows the input. A flip-flop is edge-triggered: it samples on a clock edge. Characteristic tables say what the next state is; excitation tables say what inputs are needed to force a desired transition.

GATE tests SR latch behaviour (including the forbidden input), the characteristic and excitation tables, conversions between flip-flop types, the race-around condition, sequences of states under given inputs, and setup, hold and maximum clock frequency.

Cross-coupled NOR: $Q = \overline{R + \overline{Q}}$, $\overline{Q}=\overline{S+Q}$.

With $S = R = 1$ both outputs are 0, so they are no longer complements. If both inputs then return to 0 together, the final state depends on which gate is faster (a race). Under the constraint $SR = 0$, the characteristic equation is $Q^+ = S + R'Q$.

The cross-coupled NAND latch has active-low inputs $\overline{S},\overline{R}$: $\overline{S}\,\overline{R} = 11$ holds, $01$ sets $Q = 1$, $10$ resets $Q = 0$, and $00$ is forbidden, driving both outputs to 1.

AND (or NAND) gates qualify $S,R$ or $D$ with enable. Transparent when enable $=1$ (for active-high).

$D$ input with $S=D$, $R=D'$. No forbidden combination; $Q$ follows $D$ while enabled and holds the last value when the enable drops.

Built from master-slave latches or pulse-triggered designs so the output changes only on the active clock edge (rising or falling). Types:

JK excitation.

SR and T excitation.

JK characteristic table. $JK = 00$ holds, $01$ resets, $10$ sets, $11$ toggles. The JK flip-flop is an SR flip-flop in which the forbidden input becomes "toggle". Every JK excitation row has one don't-care, because two input pairs reach each next state: from $Q = 0$, both $JK = 10$ (set) and $JK = 11$ (toggle) give $Q^+ = 1$.

Master latch samples while clock is high (or low); slave updates on the opposite phase, yielding overall edge behaviour. Modern FFs use more robust edge circuits; exam diagrams still show master-slave.

Build a JK from a gated SR latch by feeding back the outputs: $S = JQ'$ and $R = KQ$, enabled while the clock is high. With $J = K = 1$ the latch toggles, the new output feeds back, and it toggles again, as long as the clock stays high. The output oscillates whenever the clock pulse width exceeds the loop's propagation delay; the final value when the clock falls is unpredictable. This is the race-around condition. The cures are a master-slave JK (the master is closed while the slave changes) or an edge-triggered JK. A very narrow clock pulse also avoids it but is fragile.

Procedure: write the characteristic table of the target flip-flop (inputs and $Q$ to $Q^+$); for each row, read from the available flip-flop's excitation table the inputs that produce that $Q \to Q^+$; minimise those inputs as functions of the target inputs and $Q$.

Check of T from JK: $Q^+=TQ'+T'Q=T\oplus Q$. Check of D from JK: $Q^+=DQ'+DQ=D$.

For a path from flip-flop 1 through logic to flip-flop 2, both on the same clock:

The setup check uses the slowest path and depends on $T$. The hold check uses the fastest path and does not involve the clock period at all, so slowing the clock never fixes a hold violation. With clock skew $t_{\mathrm{skew}}$ (positive when the receiving FF sees the clock later):

Positive skew helps setup and hurts hold. Many timing problems ignore skew; include it only when the stem names it.

Next-state functions for a bank of FFs use the characteristic equations. EXCITE inverts any characteristic function by trying every input combination.

For a flip-flop with $k$ inputs, EXCITE does $2^k$ evaluations per row, 4 rows in all.

Cost of a conversion. Best, average and worst case are the same, because no step depends on the data. A target flip-flop with $t$ inputs has a characteristic table of $2^{t+1}$ rows (its inputs and $Q$). Each row needs one excitation lookup for the available flip-flop, or $2^k$ EXCITE evaluations if it has $k$ inputs. JK from T has 8 rows and 16 evaluations; D from JK has 4 rows and 16 evaluations. Minimisation is then a K-map on $t + 1 \le 3$ variables.

A flip-flop is a finite automaton with two states $\{0,1\}$ and inputs that determine the transition function $Q^+=\delta(Q,\textit{inputs})$. Excitation tables invert $\delta$ (with don't-cares where two inputs work).

Why the JK equation has that form. $Q^+ = 1$ when $Q = 0$ and $J = 1$ (set or toggle), or when $Q = 1$ and $K = 0$ (hold or set). That is $JQ' + K'Q$. In the same way, $Q^+ = S + R'Q$ for SR: set, or stay at 1 unless reset.

$Q^+ = 1\cdot 1 + 1\cdot 0 = 1$ (set).

T FF with $T=1$ each cycle: state sequence $0,1,0,1,\ldots$ (divide-by-2). A D flip-flop with $D = Q'$ behaves the same way, as does a JK with $J = K = 1$.

Need $K=1$, $J$ don't-care: $JK = 01$ resets and $JK = 11$ toggles, and both give 0.

If $t_{cQ}=1\,\mathrm{ns}$, $t_{logic}=3\,\mathrm{ns}$, $t_{su}=0.5\,\mathrm{ns}$, then $T\ge 4.5\,\mathrm{ns}$ (ignore skew) and $f_{\max} = 1/4.5\,\mathrm{ns} \approx 222.2\,\mathrm{MHz}$.

Take $t_{cQ} = 2$, $t_{\mathrm{logic,max}} = 5$, $t_{\mathrm{logic,min}} = 1$, $t_{su} = 1$, $t_h = 2$ (all ns).

Start at $Q = 0$ and apply $(J,K) = (1,0), (1,1), (0,0), (1,1), (0,1)$ on successive edges. The states after each edge are $1$ (set), $0$ (toggle), $0$ (hold), $1$ (toggle), $0$ (reset).

Target JK, available T, so $T = Q \oplus Q^+$ row by row. With $Q = 0$, $Q^+ = J$, so $T = J$. With $Q = 1$, $Q^+ = K'$, so $T = K$. Together $T = JQ' + KQ$. Check the toggle row $J = K = 1$: $T = Q' + Q = 1$.

A NOR latch starts with $Q = 0$. Inputs $SR = 10, 00, 01, 00, 10$ in turn give $Q = 1, 1, 0, 0, 1$. Applying $SR = 11$ would give $Q = \overline{Q} = 0$, and a following $SR = 00$ would leave the result to the race.

Common misconceptions.

All numerical timing examples that give only one $t_{cQ}$ use an idealised fixed-delay model: $t_{cQ,\min}=t_{cQ,\max}=t_{cQ}$. In a real timing analysis, use maximum propagation delay for setup and minimum clock-to-Q contamination delay for hold. If capture clock arrival minus launch clock arrival is $s$, setup requires $T\ge t_{cQ,\max}+t_{\mathrm{logic,max}}+t_{su}-s$, while hold requires $t_{cQ,\min}+t_{\mathrm{logic,min}}\ge t_h+s$.