Latches and Flip-Flops
Latches and flip-flops are bistable memory elements. A latch is level-sensitive: while the enable is asserted it follows the input. A flip-flop is edge-triggered: it samples on a clock edge.
Digital Logic · topic
Sequential circuits: flip-flops, counters and state machines
SR, D, JK and T latches and flip-flops with characteristic and excitation tables, level versus edge triggering, setup, hold and maximum clock frequency, shift registers, ripple, synchronous, mod-N, ring and Johnson counters, counter design and lockout, Moore and Mealy machines, state minimisation and sequence detectors.
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Registers and Counters
A register is a bank of flip-flops sharing a clock, often with load, clear and shift controls. A counter is a register whose state sequence follows a counted order.
Sequential Circuit Design and Finite State Machines
A synchronous sequential circuit combines combinational logic with edge-triggered flip-flops sharing a common clock. Its behaviour is a finite state machine (FSM): present state and inputs determine outputs and next state.
Sequential circuits: flip-flops, counters and state machines cheat sheets
One-page visual sheets for this topic, in the sheet library on the store. Previews are free; the full sheets come with the subject pack.