Question
Consider a system that has a cache memory unit and a memory management unit (MMU). The address input to the cache memory is a physical address. The MMU has a translation lookaside buffer (TLB). Assume that when a page is evicted from the main memory, the corresponding blocks in the cache are marked as invalid.
For a given memory reference, which of the following sequences of events can NEVER happen?
Official answer and solution
- Official answer
- B and C
- From
- Official GATE 2026 answer key
Solution
Trace the address translation and cache lookup flow for a physically addressed cache when a TLB hit or page fault occurs.
- Option (A) can happen: A valid page in main memory may not have its translation cached in the TLB (TLB miss), so the MMU walks the page table (Page table hit) to obtain the physical address, whose block is already present in the cache (Cache hit).
- Option (B) can NEVER happen: If the TLB hits, the valid physical frame translation is already present in the TLB (so the page is resident in main memory and the page table is not even accessed).
- Option (C) can NEVER happen: A TLB miss followed by a Page table miss means a page fault (the page is not in main memory). Because blocks of evicted pages are invalidated in the cache, a non-resident page cannot have a valid block in the physically addressed cache, so a Cache hit is impossible.
- Option (D) can happen: A page fault requires fetching the page from disk, and its blocks will miss in the cache.
Options (B), (C)
The answer is the one in the official GATE answer key. The solution is this site's own explanation.
Source
- Paper
- GATE 2026 Computer Science and Information Technology - Session 1 (CS1)
- Question
- 54 of 65
- Section
- Computer Science and Information Technology
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