GATE CS 2019 Q.43 (CS Q.33): Memory Management and Virtual Memory

Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are 48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how many distinct virtual addresses can be translated without any TLB miss?

$16 \times 2^{10}$

$256 \times 2^{10}$

$4 \times 2^{20}$

$8 \times 2^{20}$

Official answer and solution

Official answer: B
From: Official GATE 2019 answer key

Solution

Calculate the number of virtual addresses contained within the pages mapped by the TLB entries in a word-addressable architecture.

We are given:

Page size = $8\text{ kB} = 8 \times 1024\text{ bytes} = 8192\text{ bytes}$
Word size = $4\text{ bytes}$
Memory is word addressable, so each distinct address refers to one word.

Calculate the number of addressable words in one page:

\text{Words per page} = \frac{8192\text{ bytes}}{4\text{ bytes/word}} = 2048\text{ words} = 2^{11}\text{ words}

The TLB has $128$ valid entries. Each valid entry maps one virtual page to its corresponding physical frame.
Therefore, the maximum number of pages that can be translated without a TLB miss is $128 = 2^7$ pages.

The maximum number of distinct virtual word addresses that can be translated without any TLB miss is:

N = 128 \times 2048 = 2^7 \times 2^{11} = 2^{18}\text{ addresses}

Expressing in terms of $2^{10}$ :

N = 2^8 \times 2^{10} = 256 \times 2^{10}

Final answer

Common trap

Treating the system as byte-addressable instead of word-addressable (which would yield 128 * 8192 = 2^20 = 1024 * 2^10).

The answer is the one in the official GATE answer key. The solution is this site's own explanation.

Source

Paper: GATE 2019 Computer Science and Information Technology (CS)
Question: 43 of 65, printed as CS Q.33
Section: Computer Science and Information Technology

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